コベリティジャパン株式会社のASIC Digital Design Engineer, Staff -Sr Staff求人

Job DescriptionDate posted 08/09/2026Category EngineeringHire Type EmployeeJob ID 18307Remote Eligible NoDate Posted 08/09/2026We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou are a digital design engineer who takes pride in delivering RTL that is not only functionally correct, but also clean, synthesizable, and ready for real silicon. You enjoy working through the details—timing, CDC, lint, and design quality—because you know they matter when IP ships in customer products.You work well in a collaborative, global environment. You communicate openly with design, verification, and implementation teammates, ask thoughtful questions when specs are unclear, and are willing to learn new tools and methodologies, including AI-driven design approaches. Whether you are deepening your expertise or guiding others through complex challenges, you bring ownership, curiosity, and a practical mindset to your work.What You'll Be DoingUnderstand industry standards and functional specifications, and contribute to architecture and micro-architecture definitions for complex protocol IP coresDesign and implement RTL for digital blocks and subsystems in Verilog/SystemVerilog, balancing performance, area, power, synthesizability, and testabilityPerform basic verification and collaborate with verification teams on test planning, assertion development, functional debug, and coverage closurePerform RTL-level timing analysis during RTL development, and collaborate with implementation teams on STA, timing constraints, and synthesis as neededSupport CDC/RDC/Lint signoff readiness and collaborate on design-quality closureApply and explore AI-driven design tools and methodologies to improve design quality and automationThe Impact You Will HaveYour RTL will directly influence the quality and time-to-market of Synopsys IP used by semiconductor companies worldwideYou will reduce iteration cycles between front-end and back-end teams by delivering synthesis-ready, timing-aware designsYour collaboration will catch issues earlier, reducing costly respins and late-stage fixesThe automation you build will improve design productivity for your team and beyondYour attention to CDC/RDC/Lint readiness will strengthen product quality and reduce signoff riskWhat You'll NeedBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field4~15+ years of experience in digital design and/or RTL developmentHands-on experience designing and implementing synthesizable RTL in Verilog/SystemVerilog, with understanding of performance, area, power, and testability tradeoffsExperience with test planning, assertion development, basic verification, functional debug, and coverage closureExperience performing RTL-level timing analysis, with practical understanding of STA, timing constraints, and synthesisExperience with CDC/RDC/Lint signoff-ready design practices and design-quality closureScripting experience in Python, Tcl, Perl, or ShellWritten and oral communication skills in English and Japanese, with the ability to collaborate effectively across teamsNice to HaveDirect experience with PCIe or CXL IP design and developmentExperience with low-power design and power intent development using UPFExposure to UVM or formal verification conceptsExposure to functional safety concepts, ISO 26262, or FMEDAExperience mentoring engineers or serving as a technical lead on RTL/IP development projectsPrior experience in a global product engineering environmentWho You AreYou take ownership of your work and follow through on issues until they are properly resolvedYou collaborate openly across teams and communicate clearly in both Japanese and EnglishYou stay curious and adapt quickly to new tools, flows, and technical challengesYou balance attention to detail with practical judgment—you know when to dig deep and when to ask for helpYou share knowledge with teammates and contribute to a supportive, learning-oriented team cultureThe Team You'll Be Part OfYour recruiter will share more about the team structure and mission during the interview process.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
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