コベリティジャパン株式会社のSerDes Analog Design & Correlation, Principal Engineer - 18617求人

Overview
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You Are:
You are a visionary and detail-oriented analog designer, passionate about high-speed SerDes circuits and how they truly behave in silicon. With a deep foundation in transistor-level design, you translate specifications into robust, scalable circuits, balance power, area, and performance trade-offs, and anticipate the parasitics, mismatch, and process variation that separate simulation from reality.

What You’ll Be Doing:
* Own the design and implementation of analog macros for SerDes IP across the TX, RX, CDR, and clock paths.
* Interpret SerDes standards and architecture documents to develop detailed macro specifications.
* Optimize circuits for power, area, and performance, and oversee layout to minimize parasitics, device stress, and process variation impacts.
* Propose and execute design verification strategies using advanced simulator features, including corner and Monte Carlo analysis.
* Collaborate with digital RTL engineers on calibration, adaptation, and control algorithms for your circuits.
* Define the sim-to-silicon correlation plan for your macros, specifying what to measure, under which conditions, and why.
* Build and refine models, including extracted parasitics, behavioral models, and channel/S-parameter models, until simulation explains silicon.
* Root-cause gaps between simulation and silicon back to circuit, layout, device modeling, or package and channel effects.
* Partner with the validation team to guide test plans and interpret measurement data, feeding fixes into the next design revision.
* Mentor a small group of analog designers, and present design and correlation results for peer and customer reviews.

What You’ll Need:
* MSc with 8+ years, or PhD with 6+ years of SerDes/high-speed analog design experience, including sim-to-silicon correlation of silicon-proven designs.
* Expertise in transistor-level circuit design, with silicon-proven TX, RX, and clock-path circuits in SerDes architectures.
* In-depth knowledge of SerDes sub-circuits such as equalizers, samplers, drivers, serializers, deserializers, VCOs, phase interpolators, DLLs, PLLs, bandgap references, ADCs, and DACs.
* Experience with analog behavioral modeling using Verilog-A.
* Strong understanding of device modeling and process variation, and their impact on circuit performance.
* Experience with link and channel analysis, including S-parameter and package models.
* Familiarity with high-speed link measurements and the ability to interpret lab data statistically.
* Proficiency with EDA tools and SPICE simulators, including parasitic extraction, corner, and Monte Carlo analysis.
* Programming experience in TCL, Perl, C, Python, and MATLAB for design automation, modeling, and data analysis.