コベリティジャパン株式会社のSenior FPGA Engineer求人

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仕事内容

As part of our team, you will play a pivotal role in developing state-of-the-art FPGA solutions for high-performance PCIe applications. Your main responsibilities include prototyping and optimizing high-performance PCIe-based designs on FPGA platforms using Vivado, guiding the implementation flow through synthesis, place and route, timing closure, and hardware bring-up. You will work on simulating and verifying these designs to ensure correct functionality and behavior before FPGA implementation and hardware integration. This involves performing timing analysis and optimization across multiple clock domains, resolving setup and hold violations, and ensuring designs meet performance targets.

Collaboration is key, as you'll work closely with hardware, software, and verification teams to define requirements, evaluate design trade-offs, and deliver FPGA solutions that align with project goals. You'll be responsible for developing and executing test plans to validate the functionality, performance, and reliability of FPGA prototypes under real-world conditions.

Participation in industry events like PCI-SIG Compliance Workshops to perform official compliance testing of PCIe prototypes is also crucial. You'll ensure these prototypes meet PCIe specifications and industry standards. When compliance testing uncovers issues, you will debug and resolve hardware, protocol, and system-level issues.

Your work will significantly impact product development cycles by providing reliable FPGA prototypes that accelerate hardware and software validation processes ahead of silicon availability, identifying early integration and implementation issues.

You are expected to bring new techniques, tools, and standards to enhance our design and verification processes while maintaining exemplary documentation and offering responsive support to other teams. This position requires strong technical expertise in Verilog, RTL design, the Vivado toolchain, digital design fundamentals, and high-speed interfaces like PCIe.

募集要項

勤務地	The location for this position is Porto.
給与	-
勤務時間	-
休暇制度	-
待遇・福利厚生	-
リモートワーク	-
その他	- 応募要件: Bachelor's or Master's in Electrical Engineering, Computer Engineering, or equivalent hands-on experience. - 望ましい経験: Ideally 8+ years of FPGA design and development experience, with a strong track record of shipping working designs. Deep proficiency in Verilog and RTL design, including experience with complex state machines, pipelines, and multi-clock domain architectures. Strong command of Vivado or similar FPGA toolchains, including synthesis, implementation, and timing closure workflows. Solid understanding of digital design fundamentals: clock domain crossings, metastability, timing constraints, and static timing analysis. Experience with high-speed interfaces such as PCIe or Ethernet, including protocol-level understanding and debug. Experience with scripting languages like Python or Tcl for automation and tooling is a plus.

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